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CAT28F020
Erase-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
Programming Mode
The programming operation is initiated using the pro-
gramming algorithm of Figure 7. During the first write
cycle, the command 40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
Figure 6. A.C. Timing for Programming Operation
Program-Verify Mode
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Program-
verify operation is initiated by writing C0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify V CC . Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
VCC POWER-UP SETUP PROGRAM LATCH ADDRESS
& STANDBY COMMAND & DATA
PROGRAM
VERIFY
PROGRAM
VERIFICATION
VCC POWER-DOWN/
STANDBY
PROGRAMMING COMMAND
ADDRESSES
CE (E)
tWC
tAS
tAH
tWC
tRC
tCS
tCH
tCH
tCS
tCH
tEHQZ
OE (G)
tGHWL
tWPH
tWHWH1
tWHGL
tDF
WE (W)
tDS
tWP
tDH
tDS
tWP
tDH
tWP
tDS
tDH
tOE
tOLZ
tOH
DATA (I/O)
HIGH-Z
DATA IN
= 40H
DATA IN
DATA IN
= C0H
tLZ
tCE
VALID
DATA OUT
VCC
5.0V
0V
tVPEL
VPP
VPPH
VPPL
28F020 F07
? 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-1029, Rev. F
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